1. Field
Example embodiments relate to a semiconductor chip having a crack test circuit and a method of testing a crack of a semiconductor chip using the same. More particularly, example embodiments relate to a semiconductor chip capable of electrically inspecting a crack and a method of testing a crack of a semiconductor chip having the crack test circuit.
2. Description of the Related Art
Generally, unit processes such as a process forming a layer, an etching process, a diffusion process, a process for forming a metal wire, etc., are repeatedly performed on a silicon wafer to form a semiconductor chip.
In particular, various unit processes may be performed on a silicon wafer to form a plurality of the semiconductor chips on the silicon wafer. The semiconductor chips are generally spaced apart from each other by a desired and/or predetermined distance. A region on which the semiconductor chips are formed is referred to as a semiconductor chip region, and a region arranged between adjacent semiconductor chips is referred to as a scribe lane.
Unit cells of the semiconductor chips and a peripheral circuit for driving the unit cells are typically formed on the semiconductor chip region. In addition, pads are typically arranged on a peripheral region of a semiconductor region and are used to apply an external electric signal to the semiconductor chips.
After the semiconductor chips are formed on the silicon wafer through one or more of the unit processes, each of the semiconductor chips is packed. In order to pack the semiconductor chips a sawing process may be performed on the silicon wafer to cut along a middle line of the scribe lane to divide the silicon wafer into separate semiconductor chips. For example, the sawing process may be performed by operating a thin disk-shaped sawing blade to cut along the middle line of the scribe lane at a rapid speed.
When the silicon wafer is physically divided, as mentioned above, micro-protrusions may be formed on the various sections of the physically divided silicon wafer. It is generally difficult to obtain a surface having a uniform thickness on the section. Accordingly, a crack may be generated along a section of the scribe lane due to the sawing process. The crack may also be generated on the semiconductor chip region. In general, a defect that the crack generated on the semiconductor region by the sawing process is referred to as a chipping.
The generated crack may enable moisture to penetrate therein, which may cause a malfunction and decrease reliability of the semiconductor device on the semiconductor chip.
In a conventional method of inspecting a crack, data of the crack may be obtained from an image of a section photographed by an optical instrument such as an optical microscope, for example. This data may then be processed and analyzed. However, inspecting a crack according to the above-described conventional method may take a significant amount of time. Further, it may be difficult to inspect minute cracks using the above-described conventional method.
In another conventional method of inspecting a crack, the crack is electrically inspected. The extra pads are connected to different end portions of the inspection line. An electrical signal may be applied to the extra pads and an outputted current, or a resistance, may be detected to inspect the crack. The inspection line surrounds the peripheral region of the semiconductor chip region. Therefore, if a crack is generated, a portion of the inspection line may be damaged or broken, which may result in an increased resistance of the inspection line. Accordingly, the current or the resistance between the extra pads may be detected to assure the detected value is in an allowable range.
However, in order to implement the above-described method, at least two extra pads, which may be connected to different end portions of the inspection line, are required. Therefore, this conventional method decreases the integration degree of the semiconductor chips because extra pads are required.